1. Field of the Invention
The present invention relates to an apparatus and a method for reducing memory access conflict, and more particularly, to an apparatus and a method for minimizing memory access conflict when a plurality of data processing elements simultaneously access a memory page in a parallel data processing array including a plurality of the data processing elements for processing massive quantity of multimedia data.
This work was partly supported by the IT R&D program of MIC/IITA [2006-S-048-02, Embedded DSP Platform for Audio/Video Signal Processing].
2. Description of the Related Art
Developments in the information technology (IT) have lead to a dramatic increase in the number of multimedia apparatuses processing multimedia data such as audio and video, including not only portable devices but also home appliances. There are various types of multimedia apparatuses available, including digital video disc (DVD) players, multimedia players supporting motion picture experts group 2 (MPEG-2) data compression technologies, cellular phones capable of playing back motion picture, high-definition televisions (HDTV), etc. Video playback and audio playback for the multimedia apparatuses require massive amounts of data. For example, when each pixel of an image of a resolution of 1920 by 1200 is expressed in 24 bit, 1.66 Gbps transmission speed is required to transmit 30 frames per second in a serial bitstream. The more frame rate requires the higher transmission speed. Accordingly most of current video and audio signals employ highly compressing technologies.
There are numerous types of compressing technologies, including MPEG-2, MPEG-4, a H.264, bit sliced arithmetic coding (BSAC), advanced audio coding plus (AAC+), etc. In order to utilize the above-described compressing technologies, a hardware capable of encoding/decoding motion pictures is required. Therefore, most of the present mobile and home multimedia devices include a very large scale integration (VSLI) for a multimedia codec to encode/decode motion pictures in real-time. Although data processing performance required by the codec VLSI depends on complexity or characteristics of a multimedia codec algorithm, recent multimedia codec needs 0.6 giga instructions per second (GIPS) through 1.5 GIPS, and it is anticipated that the required data processing performance will reach 2 GIPS through 5 GIPS within a few years.
A method for implementing the various multimedia codecs into hardware, while obtaining a high performance, is to adopt a processor array structure. While a programmable processor enables the various multimedia codecs to be implemented in a short time, an array structure programmable processor has a potential of a high performance of multimedia data processing. Also, since multimedia data processing has characteristics of repetition of the same operation for a series of data stream, it is easy to make data processed in parallel. Data processing in parallel means that data processing tasks can be independently allocated into a plurality of processors and the allocated tasks can be performed simultaneously.
A processor array for multimedia data processing generally includes a large capacity memory having a structure to which a plurality of data processing elements can simultaneously access. Accesses by more than two data processing elements to the same physical memory may cause a conflict. To resolve the conflict, a memory access arbiter processes memory accesses in turn by sacrificing clock cycles, so that each of the data processing elements can access the memory normally. As the number of data processing elements capable of accessing the same physical memory increases, the number of conflicts also increases continuously, so that overall multimedia data process performances are lowered.